Analog-to-digital converters (ADCs) convert time-discrete analog input values to a digital form. A type of ADC, the successive approximation register (SAR) ADC, digitizes the analog input values using a successive approximation search algorithm. While the internal circuitry of the SAR ADC may run at a higher frequency (such as several megahertz (MHz), for example), the sample rate of the SAR ADC is generally a fraction of that frequency (such as several kilohertz (kHz), for example) due to the successive approximation search algorithm used. For example, normally each bit of the SAR ADC is fully realized prior to proceeding on to the next bit.
In general, many of today's microcontroller products can have several SAR ADCs on a single chip. In some high-end products, up to 20 or more ADC instances may be placed on the chip. To reduce the amount of ADC instances, a passive sample and hold (SH) ADC structure can be used with a time multiplexed operating scheme.
In some cases, an external voltage reference may be provided to the ADC. This external reference can be a direct supply to the ADC and also a supply to the sensors of the application, for instance. In such an application, the output of the sensors can be a ratiometric voltage based on the supply, which is converted by the ADC to a digital form for use by the microcontroller. The absolute value of the reference/supply voltage is generally cancelled in this scheme, making the external ADC reference desirable. In another implementation, the voltage reference may be provided by the ADC.
However, gain error can occur within passive SH ADCs, due to the use of two different capacitors: one for analog input sampling and one for the conversion process (internal digital-to-analog conversion). The gain error is associated with a mismatch of these two capacitors. In some cases, an on-chip reference voltage can provide at least a partial remedy for the gain error. Generally though, an on chip reference uses a reference buffer for the switched capacitor load of the ADC. This buffer uses chip area and current, and can produce noise. Further, the use of an on-chip reference disallows many of the benefits of an external reference, including those mentioned above.
The patent application US 2015/0002321 A1 shows a successive approximation register ADC that includes an SAR comparator circuit. The SAR comparator circuit includes a plurality of capacitors and a calibration circuit. The calibration of switches to alter the charge may be varied over time to alter the amplitude of the input signal providing a time-varying input signal that may be used to calibrate the ADC. This ensures that mismatch errors in the DAC are correctable.
The U.S. Pat. No. 8,766,833 B1 shows a system for calibrating a circuit by coupling a programmable reference voltage to a reference node of a DAC.
The patent application US 2011/0215956 discloses a charge redistribution type successive approximation routine (SAR) analog-to-digital converter (ADC), in which capacitors are coupled to one of an analog input signal, an upper reference voltage and a lower reference voltage. The ADC comprises an offset correction circuit.
The U.S. Pat. No. 7,170,439 B1 discloses a self-calibration circuit for a capacitance mismatch. The Setup-and-Hold circuit comprises a capacitor array (CT) that is used for sampling and as DAC capacitor.